I always wanted to learn about how programmable logic actually worked. I liked the idea of connecting gates together without the use of soldering iron or a breadboard. Especially since some people are using it to crack GSM’s encryption or do other interesting stuff.
For a beginner, CPLDs seemed a more natural choice than FPGAs. They feature an on-chip rewritable non-volatile flash storage for power-on configuration, some representation of logic fabric, and a number of general-purpose pins that can be freely assigned. They are also smaller, cheaper and come in easier to solder packages. I had one CPLD part in my inventory for some time, a Xilinx’s XC9536XL. It’s probably the smallest of the programmable logic gate ICs on the market – it features 36 “macrocells”. To give you a sense of scale, you can roughly fit a 32-bit counter inside with some supporting circuity. I decided to learn first-hand about what’s all that fuss with “faster-than-light” programmable gate arrays and design a simple board for experiments.
The board I built is nothing fancy – all the device’s pins are routed to pin headers on the sides on the board. JTAG pins are put in one place, and the so-called clock inputs are wired to the quartz crystal/generator stands. The only other visible IC is an 74HCT02 quad NOR gate acting as a clock amplifier for the quartz crystal stand. If you don’t know the difference between a “quartz crystal” and a “quartz oscillator”, there is an interesting article on the difference here: Quartz Crystals and Oscillators.
Top side’s view, with a 25.175MHz crystal oscillator plugged in:
If you will take a closer look, you can see some interesting pattern on the black plastic base of the pin headers. I kid you not, I did not alter them in any way. Here is a close-up shot:
I used this board in a number of projects afterwards. I built a JTAG “cable” to program it: Xilinx Parallel Cable III. And I made a simple test to see if it actually works: Binary counter in Verilog. You will also see it in a more ambitious project, a VGA monitor, but that’s still underway.